STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Revision history
Table 215.
Document revision history (continued)
Date Revision Changes
28-Jul-2008 5
Developed polynomial form updated in Section 3.2: CRC main features on
page 50.
Figure 4: Power supply overview on page 53 modified.
Section 4.1.2: Battery backup domain on page 54 modified.
Section 6.2.5: LSI clock on page 80 specified.
Section 8.1.4: Alternate functions (AF) on page 141 clarified.
Note added to Table 41: TIM2 alternate function remapping on page 156.
Bits are write-only in Section 10.4.2: DMA interrupt flag clear register
(DMA_IFCR) on page 192.
Register name modified in Section 11.3.1: ADC on-off control on page 201.
Recommended sampling time given in Section 11.10: Temperature sensor
on page 217.
Bit attributes modified in Section 11.12.1: ADC status register (ADC_SR) on
page 219.
Note modified for bits 23:0 in Section 11.12.4: ADC sample time register 1
(ADC_SMPR1) on page 225.
Note added in Section 12.2: DAC main features on page 233.
Formula updated in Section 12.3.5: DAC output voltage on page 237.
DBL[4:0] description modified in Section 13.3.19: TIMx and external trigger
synchronization on page 290.
Figure 81 on page 273 and Figure 127 on page 337 modified.
Section 23.5.3: SPI status register (SPI_SR) on page 617 modified.
Closing the communication on page 633 updated.
Notes added to Section 24.6.8: Clock control register (I2C_CCR) on
page 650. TCK replaced by T PCLK1 in Section 24.6.8 and Section 24.6.9.
OVR changed to ORE in Figure 259: USART interrupt mapping diagram on
page 682.
Section 25.6.1: Status register (USART_SR) on page 683 updated.
Slave select (NSS) pin management on page 590 clarified.
Small text changes.
Doc ID 13902 Rev 9 987/995