STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Connectivity line devices: reset and clock control (RCC)
Figure 11.
Clock tree
40 kHz
LSI
RC
to independent watchdog
IWDGCLK
OSC32_IN
OSC32_OUT
32.768 kHz
LSE
OSC
LSI
to RTC
LSE
RTCCLK
/128
RTCSEL[1:0]
HSE
CSS
to Flash prog. IF
FLITFCLK
OSC_IN
OSC_OUT
XT1 to MCO
3-25 MHz
HSE
OSC
8 MHz
HSI RC
/2
/1,2,3....
..../15, /16
PLLSCR
PREDIV1
PREDIV1SCR
PLLMUL
x4, x5,... x9,
x6.5
HSI
PLLCLK
SW
PLLVCO
USB prescaler
/2,3
SYSCLK
system clock
PREDIV2
PLL2MUL
x8, x9,... x14,
x16, x20
OTGFSCLK
48 MHz
to USB OTG FS
to I2S2 interface
/1,2,3....
..../15, /16
PLL3MUL PLL2CLK
to MCO
x8, x9,... x14,
x16, x20
PLL3VCO
PLL3CLK to MCO
to I2S3 interface
MCO
MCO[3:0]
HSE
HSI
PLLCLK/2
PLL2CLK
PLL3CLK/2
PLL3CLK
XT1
APB1 prescaler
/1, 2, 4, 8, 16
HCLK to AHB bus, core memory and DMA
/2 to Cortex System timer
FCLK Cortex free running clock
36 MHz max
Peripheral clock enable
PCLK1
to APB1 peripherals
SYSCLK
72 MHz max.
(see note1)
AHB prescaler
/1,/2 ../512
TIM2,3,4,5,6,7
If(APB1 prescaler =1) x1
else x2
Peripheral clock enable
to TIM2,3,4,5,
6 & 7
TIMxCLK
APB2 prescaler
/1, 2, 4, 8, 16
72 MHz max
Peripheral clock enable
PCLK2
to APB2 peripherals
Ethernet
PHY
ETH_MII_TX_CLK
ETH_MII_RX_CLK
/2, /20
MACTXCLK
MII_RMII_SEL
in AFIO_MAPR
MACRXCLK
to Ethernet MAC
TIM1
If(APB2 prescaler =1) x1
else x2
Peripheral clock enable
ADC prescaler
/2, 4, 6, 8
ADCCLK
14 MHz max
to TIM1
TIMxCLK
to ADC1,2
MACRMIICLK
ai15699c
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.
The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the
application in the choice of the external crystal or oscillator to run the core and peripherals
at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB
OTG FS.
A single 25 MHz crystal can clock the entire system and all peripherals including the
Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance,
an audio crystal can be used. In this case, the I2S master clock can generate all standard
sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.
For more details about clock configuration for applications requiring Ethernet, USB OTG FS
and/or I 2 S (audio), please refer to "Appendix A Applicative block diagrams" in your
connectivity line device datasheet.
Doc ID 13902 Rev 9 107/995