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DMA controller (DMA) RM0008 10.3.7 DMA request mapping DMA1 controller The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering DMA1, this means that only one request must be enabled at a time. Refer to Figure 23: DMA1 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. Figure 23. DMA1 request mapping Peripheral request signals ADC1 TIM2_CH3 TIM4_CH1 HW request 1 SW trigger (MEM2MEM bit) Channel 1 Fixed hardware priority High priority USART3_TX TIM1_CH1 TIM2_UP TIM3_CH3 SPI1_RX USART3_RX TIM1_CH2 TIM3_CH4 TIM3_UP SPI1_TX USART1_TX TIM1_CH4 TIM1_TRIG TIM1_COM TIM4_CH2 SPI/I2S2_RX I2C2_TX USART1_RX TIM1_UP SPI/I2S2_TX TIM2_CH1 TIM4_CH3 I2C2_RX USART2_RX TIM1_CH3 TIM3_CH1 TIM3_TRIG I2C1_TX Channel 1 EN bit HW request 2 Channel 2 SW trigger (MEM2MEM bit) Channel 2 EN bit HW request 3 Channel 3 SW trigger (MEM2MEM bit) Channel 3 EN bit HW request 4 Channel 4 SW trigger (MEM2MEM bit) Channel 4 EN bit HW request 5 Channel 5 SW trigger (MEM2MEM bit) Channel 5 EN bit HW REQUEST 6 Channel 6 SW TRIGGER (MEM2MEM bit) Channel 6 EN bit internal DMA1 request USART2_TX TIM2_CH2 TIM2_CH4 TIM4_UP I2C1_RX HW request 7 Channel 7 SW trigger (MEM2MEM bit) Channel 7 EN bit Low priority Table 57 lists the DMA requests for each channel. 188/995 Doc ID 13902 Rev 9
RM0008 DMA controller (DMA) Table 57. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI/I 2 S SPI1_RX SPI1_TX SPI/I2S2_RX SPI/I2S2_TX USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I 2 C I2C2_TX I2C2_RX I2C1_TX I2C1_RX TIM1 TIM1_CH1 TIM1_CH2 TIM1_CH4 TIM1_TRIG TIM1_COM TIM1_UP TIM2 TIM2_CH3 TIM2_UP TIM2_CH1 TIM3 TIM3_CH3 TIM3_CH4 TIM3_UP TIM1_CH3 TIM3_CH1 TIM3_TRIG TIM2_CH2 TIM2_CH4 TIM4 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP DMA2 controller Note: The 5 requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4, DAC_Channel[1,2]and SDIO) are simply logically ORed before entering to the DMA2, this means that only one request must be enabled at a time. Refer to Figure 24: DMA2 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. The DMA2 controller and its relative requests are available only in high-density and connectivity line devices. Doc ID 13902 Rev 9 189/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Pre
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Ethernet (ETH): media access
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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