STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Flexible static memory controller (FSMC)
Table 93.
Bit
number
FSMC_BCRx bit fields
Bit name
Value to set
31-15 0x0000
14-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 -
6 FACCEN -
5-4 MWID As needed
3-2 MTYP As needed, exclude 10 (NOR Flash)
1 MUXEN 0x0
0 MBKEN 0x1
Table 94.
Bit
number
FSMC_TCRx bit fields
Bit name
Value to set
31-16 0x0000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST+3 HCLK cycles for read accesses).
This value cannot be 0 (minimum is 1).
7-4 0x0
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) .
Doc ID 13902 Rev 9 419/995