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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

USB on-the-go full-speed (OTG_FS)<br />

OTG_FS USB configuration register (OTG_FS_GUSBCFG)<br />

Address offset: 0x00C<br />

Reset value: 0x0000 0A00<br />

This register can be used to configure the core after power-on or a changing to Host mode<br />

or Device mode. It contains USB <strong>and</strong> USB-PHY related configuration parameters. The<br />

application must program this register before starting any transactions on either the AHB or<br />

the USB. Do not make changes to this register after the initial programming.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

CTXPKT<br />

FDMOD<br />

FHMOD<br />

Reserved<br />

NPTXRWEN<br />

TRDT<br />

HNPCAP<br />

SRPCAP<br />

Reserved<br />

TOCAL<br />

rw rw rw rw rw<br />

r/rw<br />

r/rw<br />

rw<br />

Bits 31:20 Reserved.<br />

Bit 31 CTXPKT: Corrupt Tx packet<br />

This bit is for debug purposes only. Never set this bit to 1.<br />

Note: Accessible in both Device <strong>and</strong> Host modes.<br />

Bit 30 FDMOD: Force device mode<br />

Writing a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input pin.<br />

0: Normal mode<br />

1: Force device mode<br />

After setting the force bit, the application must wait at least 25 ms before the change takes<br />

effect.<br />

Note: Accessible in both Device <strong>and</strong> Host modes.<br />

Bit 29 FHMOD: Force host mode<br />

Writing a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin.<br />

0: Normal mode<br />

1: Force host mode<br />

After setting the force bit, the application must wait at least 25 ms before the change takes<br />

effect.<br />

Note: Accessible in both Device <strong>and</strong> Host modes.<br />

Bits 28:15 Reserved<br />

Bit 14 NPTXRWEN: Reserved non-periodic TxFIFO rewind enable<br />

In Host mode, this bit should be set when only one channel is enabled. When this bit is set, the<br />

core automatically retries an OUT transaction in case of NAK or timeout, without interrupting<br />

the application.<br />

In Device mode, this bit should be set only when one non-periodic IN endpoint is enabled at<br />

any point in time, as can happen in mass storage applications. When this bit is enabled, the<br />

core can internally h<strong>and</strong>le the timeout on non-periodic endpoints without application<br />

intervention.<br />

Note: Accessible in both Device <strong>and</strong> Host modes.<br />

Doc ID 13902 Rev 9 727/995

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