STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Controller area network (bxCAN)
Figure 206. Event flags and interrupt generation
RQCP0
CAN_TSR RQCP1 +
RQCP2
CAN_IER
TMEIE
&
TRANSMIT
INTERRUPT
CAN_RF0R
FMP0
FULL0
FMPIE0
FFIE0
&
&
+
FIFO 0
INTERRUPT
FOVR0
FOVIE0
&
CAN_RF1R
FMP1
FULL1
FMPIE1
FFIE1
&
&
+
FIFO 1
INTERRUPT
FOVR1
FOVIE1
&
ERRIE
EWGF
EWGIE
&
CAN_ESR
EPVF
BOFF
1LEC6
EPVIE
BOFIE
LECIE
&
&
&
+
ERRI
CAN_MSR
&
+
STATUS CHANGE
ERROR
INTERRUPT
CAN_MSR
WKUI
SLAKI
WKUIE
SLKIE
&
&
●
●
●
The transmit interrupt can be generated by the following events:
– Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.
– Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.
– Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.
The FIFO 0 interrupt can be generated by the following events:
– Reception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’.
– FIFO0 full condition, FULL0 bit in the CAN_RF0R register set.
– FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.
The FIFO 1 interrupt can be generated by the following events:
– Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.
– FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
– FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.
Doc ID 13902 Rev 9 561/995