STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Figure 303. Reception with false carrier indication
MII_RX_CLK
MII_RX_DV
MII_RXD[3:0]
XX
XX
XX
XX
0E XX XX XX XX
MII_RX_ERR
ai15636
27.5.4 MAC interrupts
Interrupts can be generated from the MAC core as a result of various events.
The ETH_MACSR register describes the events that can cause an interrupt from the MAC
core. You can prevent each event from asserting the interrupt by setting the corresponding
mask bits in the Interrupt Mask register.
The interrupt register bits only indicate the block from which the event is reported. You have
to read the corresponding status registers and other registers to clear the interrupt. For
example, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on-
LAN frame is received in Power-down mode. You must read the ETH_MACPMTCSR
Register to clear this interrupt event.
Figure 304. MAC core interrupt masking scheme
TSTS
TSTIM
AND
TSTI
OR
Interrupt
PMTS
PMTIM
AND
PMTI
ai15637
27.5.5 MAC filtering
Address filtering
Address filtering checks the destination and source addresses on all received frames and
the address filtering status is reported accordingly. Address checking is based on different
parameters (Frame filter register) chosen by the application. The filtered frame can also be
identified: multicast or broadcast frame.
Address filtering uses the station's physical (MAC) address and the Multicast Hash table for
address checking purposes.
Doc ID 13902 Rev 9 865/995