STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
USB on-the-go full-speed (OTG_FS)
26.14 OTG_FS control and status registers
By reading from and writing to the control and status registers (CSRs) through the AHB
slave interface, the application controls the OTG_FS controller. These registers are 32 bits
wide, and the addresses are 32-bit block aligned. CSRs are classified as follows:
● Core global registers
● Host-mode registers
● Host global registers
● Host port CSRs
● Host channel-specific registers
● Device-mode registers
● Device global registers
● Device endpoint-specific registers
● Power and clock-gating registers
● Data FIFO (DFIFO) access registers
Only the Core global, Power and clock-gating, Data FIFO access, and Host port control and
status registers can be accessed in both Host and Device modes. When the OTG_FS
controller is operating in one mode, either Device or Host, the application must not access
registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is
generated and reflected in the Core interrupt register (MMIS bit in the OTG_FS_GINTSTS
register). When the core switches from one mode to the other, the registers in the new mode
of operation must be reprogrammed as they would be after a power-on reset.
26.14.1 CSR memory map
The Host and Device mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
Doc ID 13902 Rev 9 717/995