STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Revision history
Table 215.
Document revision history (continued)
Date Revision Changes
22-Jun-2009 9
Reference manual updated to support also STM32F105xx/STM32F107xx
connectivity line devices.
Memory and bus architecture section: Embedded boot loader updated.
Section 3.3: CRC functional description updated.
Note modified in Section 4.1.2: Battery backup domain.
Connectivity line devices: reset and clock control (RCC) section: Figure 10:
Reset circuit updated. PLL1 changed to PLL. Note added to BDP bit
description in Section 4.4.1: Power control register (PWR_CR). Table 48:
SPI3 remapping corrected.
DMA section: Table 55: Programmable data width & endian behavior (when
bits PINC = MINC = 1) updated, Section 10.3.1: DMA transactions and
Pointer incrementation on page 184 modified. DMA channel x peripheral
address register (DMA_CPARx) (x = 1 ..7) and DMA channel x memory
address register (DMA_CMARx) (x = 1 ..7) must not be written when the
channel is enabled.
Advanced-control timer section: Section 13.3.12: Using the break function
on page 279 updated. BKE and BKP bit descriptions updated in
Section 13.4.18: TIM1&TIM8 break and dead-time register (TIMx_BDTR).
CC1IF bit description modified in Section 13.4.5: TIM1&TIM8 status register
(TIMx_SR) and Section 14.4.5: TIMx status register (TIMx_SR).
Note added to Table 72: TIMx Internal trigger connection and Table 76: TIMx
Internal trigger connection on page 359.
Table 92: NOR Flash/PSRAM supported memories and transactions on
page 416 and Single-burst transfer modified.
Register numbering and address offset corrected in Section 20.9.6: SDIO
response 1..4 register (SDIO_RESPx) on page 500.
In Section 22: Controller area network (bxCAN): DBF bit reset value and
access type modified, small text changes.
SPI section: note added in Section 23.2.2: I 2 S features. Slave select (NSS)
pin management clarified. Note added at the end of Section 23.3.3: SPI
master mode and Section 23.3.4: Simplex communication.
Audio frequency precision tables 166 and 167 added to Section 23.4.3:
Clock generator on page 607 and audio sampling frequency range
increased to 96 kHz.
Arbitration lost (ARLO) on page 634 specified.
USART section: Description of “1.5 stop bits” updated in Configurable stop
bits, RTS flow control corrected. Procedure sequence modified in
Section 25.3.2: Transmitter. How to derive USARTDIV from USART_BRR
register values modified. Section 25.3.5: USART receiver’s tolerance to
clock deviation added. Section 25.3.11: Smartcard and Section 25.3.10:
Single-wire half-duplex communication updated. Bit 12 description modified
in Section 25.6.4: Control register 1 (USART_CR1).
Debug support (DBG) section:
– Figure 320: Block diagram of STM32F10xxx-level and Cortex-M3-level
debug support updated
– Section 29.15: ETM (Embedded Trace Macrocell) added
– Figure 323: TPIU block diagram updated
–in DBGMCU_IDCODE, REV_ID(15:0) updated for connectivity line
devices (revision Z added).
Section 26: USB on-the-go full-speed (OTG_FS) revised. Small text
changes.
Doc ID 13902 Rev 9 991/995