STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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USB on-the-go full-speed (OTG_FS) RM0008 configured to generate port interrupts. The overcurrent ISR must promptly disable the V BUS generation. Figure 263. USB host only connection V DD (2) GPIO+IRQ STM32F105xx STM32F107xx PA9 OSC_IN OSC_OUT GPIO PA11 PA12 EN Overcurrent ST20x2 Current limited power distribution switch (1) 5V Pwr VBUS DM DP V SS USB Std-A connector ai17117 1. ST20x2 only needed if the application has to support a V BUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. V DD range is between 2 V and 3.6 V. 26.6.1 SRP-capable host SRP support is available through the SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_FS_GUSBCFG). With the SRP feature enabled, the Host can save power by switching off the V BUS power while the USB session is suspended. The SRP host mode program model is described in detail in the A-device session request protocol) section. 26.6.2 USB host states Host port power On-chip 5 V V BUS generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch, must be added externally to drive the 5 V V BUS line. The external charge pump can be driven by any GPIO output. When the application decides to power on V BUS using the chosen GPIO, it must also set the port power bit in the host port control and status register (PPWR bit in OTG_FS_HPRT). V BUS valid The V BUS input ensures that valid V BUS levels are supplied by the charge pump during USB operations. Any unforeseen V BUS voltage drop below the V BUS valid threshold (4.25 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in OTG_FS_GOTGINT). The application is then required to remove the V BUS power and clear the port power bit. The charge pump overcurrent flag can also be used to prevent electrical damage. Connect the overcurrent flag output from the charge pump to any GPIO input and configure it to generate a port interrupt on the active level. The overcurrent ISR must promptly disable the V BUS generation and clear the port power bit. 704/995 Doc ID 13902 Rev 9
RM0008 USB on-the-go full-speed (OTG_FS) Host detection of a peripheral connection Even if USB peripherals or B-devices can be attached at any time, the OTG_FS will not detect any bus connection until V BUS is no longer sensed at a valid level (over 4.75 V). When V BUS is at a valid level and a remote B-device is attached, the OTG_FS Core issues an host port interrupt triggered by the device connected bit in the host port control and status register (PCDET bit in OTG_FS_HPRT). Host detection of peripheral a disconnection The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit in OTG_FS_GINTSTS). Host enumeration After detecting a peripheral connection the host must start the enumeration process by sending USB reset and configuration commands to the new peripheral. Before starting to drive a USB reset, the application waits for the OTG interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), which indicates that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). The application drives a USB reset signaling (single-ended zero) over the USB by keeping the port reset bit set in the host port control and status register (PRST bit in OTG_FS_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes care of the timing count and then of clearing the port reset bit. Once the USB reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (PENCHNG bit in OTG_FS_HPRT). This informs the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and status register (PSPD bit in OTG_FS_HPRT) and that the host is starting to drive SOFs (FS) or Keep alives (LS). The Host is now ready to complete the peripheral enumeration by sending peripheral configuration commands. Host suspend The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register (PSUSP bit in OTG_FS_HPRT). The OTG_FS Core stops sending SOFs and enters the suspended state. The suspended state can be optionally exited on the remote device’s initiative (remote wakeup). In this case the remote wakeup interrupt (WKUPINT bit in OTG_FS_GINTSTS) is generated upon detection of a remote wakeup signaling, the port resume bit in the host port control and status register (PRES bit in OTG_FS_HPRT) self-sets, and resume signaling is automatically driven over the USB. The application must time the resume window and then clear the port resume bit to exit the suspended state and restart the SOF. If the suspended state is exited on the host’s initiative, the application must set the port resume bit to start resume signaling on the host port, time the resume window and finally clear the port resume bit. 26.6.3 Host channels The OTG_FS core instantiates 8 host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 8 transfer requests at the Doc ID 13902 Rev 9 705/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Interrupts and events Table
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Revision history 30 Revision
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RM0008 Please Read Carefully: Infor
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