STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

USB on-the-go full-speed (OTG_FS)
RM0008
OTG_FS device control OUT endpoint 0 control register
(OTG_FS_DOEPCTL0)
Address offset: 0xB00
Reset value: 0x0000 8000
This section describes the device control OUT endpoint 0 control register. Nonzero control
endpoints use registers for endpoints 1–15.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPENA
EPDIS
Reserved
SNAK
CNAK
Reserved
Stall
SNPM
EPTYP
NAKSTS
Reserved
USBAEP
MPSIZ
Reserved
w r w w rs rw r r r r r r
Bit 31 EPENA: Endpoint enable
The application sets this bit to start transmitting data on endpoint 0.
The core clears this bit before setting any of the following interrupts on this endpoint:
– SETUP phase done
– Endpoint disabled
– Transfer completed
Bit 30 EPDIS: Endpoint disable
The application cannot disable control OUT endpoint 0.
Bits 29:28 Reserved
Bit 27 SNAK: Set NAK
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the transmission of NAK handshakes on an endpoint.
The core can also set this bit on a Transfer completed interrupt, or after a SETUP is received
on the endpoint.
Bit 26 CNAK: Clear NAK
A write to this bit clears the NAK bit for the endpoint.
Bits 25:22 Reserved
Bit 21 STALL: STALL handshake
The application can only set this bit, and the core clears it, when a SETUP token is received
for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes
priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with
an ACK handshake.
Bit 20 SNPM: Snoop mode
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the
correctness of OUT packets before transferring them to application memory.
Bits 19:18 EPTYP: Endpoint type
Hardcoded to 2’b00 for control.
766/995 Doc ID 13902 Rev 9