STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Universal synchronous asynchronous receiver transmitter (USART)
3 It is advised that TE and RE are set in the same instruction in order to minimize the setup
and the hold time of the receiver.
4 The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
Figure 248. USART example of synchronous transmission
RX
TX
Data out
Data in
USART
Synchronous device
(e.g. slave SPI)
SCLK
Clock
Figure 249. USART data clock timing diagram (M=0)
Idle or preceding
transmission
Start
M=0 (8 data bits)
Stop
Idle or next
transmission
Clock (CPOL=0, CPHA=0)
*
Clock (CPOL=0, CPHA=1)
*
Clock (CPOL=1, CPHA=0)
*
Clock (CPOL=1, CPHA=1)
*
Data on TX
(from master)
0 1 2 3 4 5 6 7
Start LSB MSB Stop
Data on RX 0 1 2 3 4 5 6 7
(from slave)
LSB
MSB
*
Capture Strobe
* LBCL bit controls last data clock pulse
Doc ID 13902 Rev 9 673/995