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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Secure digital input/output interface (SDIO)<br />

5. Send CMD24 (WRITE_BLOCK) as follows:<br />

a) Program the SDIO data length register (SDIO data timer register should be<br />

already programmed before the card identification process)<br />

b) Program the SDIO argument register with the address location of the card where<br />

data is to be transferred<br />

c) Program the SDIO comm<strong>and</strong> register: CmdIndex with 24 (WRITE_BLOCK);<br />

WaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO<br />

card host enabled to send a comm<strong>and</strong>). Other fields are at their reset value.<br />

d) Wait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control<br />

register: DTEN with ‘1’ (SDIO card host enabled to send data); DTDIR with ‘0’<br />

(from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’<br />

(DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care.<br />

e) Wait for SDIO_STA[10] = DBCKEND<br />

6. Check that no channels are still enabled by polling the DMA Enabled Channel Status<br />

register.<br />

20.4 Card functional description<br />

20.4.1 Card identification mode<br />

While in card identification mode the host resets all cards, validates the operation voltage<br />

range, identifies cards <strong>and</strong> sets a relative card address (RCA) for each card on the bus. All<br />

data communications in the card identification mode use the comm<strong>and</strong> line (CMD) only.<br />

20.4.2 Card reset<br />

The GO_IDLE_STATE comm<strong>and</strong> (CMD0) is the software reset comm<strong>and</strong> <strong>and</strong> it puts the<br />

MultiMediaCard <strong>and</strong> SD memory in the Idle state. The IO_RW_DIRECT comm<strong>and</strong> (CMD52)<br />

resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the highimpedance<br />

state <strong>and</strong> the cards are initialized with a default relative card address<br />

(RCA=0x0001) <strong>and</strong> with a default driver stage register setting (lowest speed, highest driving<br />

current capability).<br />

20.4.3 Operating voltage range validation<br />

All cards can communicate with the SDIO card host using any operating voltage within the<br />

specification range. The supported minimum <strong>and</strong> maximum V DD values are defined in the<br />

operation conditions register (OCR) on the card.<br />

Cards that store the card identification number (CID) <strong>and</strong> card specific data (CSD) in the<br />

payload memory are able to communicate this information only under data-transfer V DD<br />

conditions. When the SDIO card host module <strong>and</strong> the card have incompatible V DD ranges,<br />

the card is not able to complete the identification cycle <strong>and</strong> cannot send CSD data. For this<br />

purpose, the special comm<strong>and</strong>s, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41<br />

for SD Memory), <strong>and</strong> IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a<br />

mechanism to identify <strong>and</strong> reject cards that do not match the V DD range desired by the<br />

SDIO card host. The SDIO card host sends the required V DD voltage window as the<br />

oper<strong>and</strong> of these comm<strong>and</strong>s. Cards that cannot perform data transfer in the specified range<br />

disconnect from the bus <strong>and</strong> go to the inactive state.<br />

Doc ID 13902 Rev 9 471/995

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