STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Flexible static memory controller (FSMC)
RM0008
Table 99.
FSMC_TCRx bit fields
Bit number Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x1 if extended mode is set
27-16 0x000
15-8 DATAST
7-4 0x0
3-0 ADDSET
Duration of the access second phase (DATAST+3 HCLK cycles) in
read. This value can not be 0 (minimum is 1)
Duration of the access first phase (ADDSET+1 HCLK cycles) in
read.
Table 100.
Bit
number
FSMC_BWTRx bit fields
Bit name
Value to set
31-30 0x0
29-28 ACCMOD 0x1 if extended mode is set
27-16 0x000
15-8 DATAST
7-4 0x0
3-0 ADDSET
Duration of the access second phase (DATAST+1 HCLK cycles) in
write. This value can not be 0 (minimum is 1).
Duration of the access first phase (ADDSET+1 HCLK cycles) in
write.
Note:
The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its
content is don’t care.
424/995 Doc ID 13902 Rev 9