STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Revision history
Table 215.
Document revision history (continued)
Date Revision Changes
20-Nov-2007 2
Figure 238: USART block diagram modified.
Procedure modified in Character reception on page 661.
In Section 25.3.4: Fractional baud rate generation:
– Equation legend modified
– Table 174: Error calculation for programmed baud rates modified
– Note added
Small text changes. In CAN bit timing register (CAN_BTR) on page 571, bit
15 is reserved.
Flash memory organization corrected, Table 3: Flash module organization
(medium-density devices) modified in Section 2.3.3: Embedded Flash
memory.
Note added below Figure 4: Power supply overview in Section 4.1: Power
supplies.
RTCSEL[1:0] bit description modified in Backup domain control register
(RCC_BDCR).
Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR in
Table 15: RCC register map and reset values.
Impedance value specified in A.4: Voltage glitch on ADC input 0 on
page 500.
In Section 23.5.1: SPI control register 1 (SPI_CR1) (not used in I 2 S mode),
BR[2:0] description corrected.
Prescaler buffer behavior specified when an update event occurs (see
upcounting mode on page 323, Downcounting mode on page 326 and
Center-aligned mode (up/down counting) on page 328).
AWDCH[4:0] modified in Section 11.12.2: ADC control register 1
(ADC_CR1) and bits [26:24] are reserved in Section 11.12.4: ADC sample
time register 1 (ADC_SMPR1).
CAN_BTR bit 8 is reserved in Table 164: bxCAN register map and reset
values. CAN master control register (CAN_MCR) on page 562 corrected.
V REF+ range corrected in Table 60: ADC pins and in On 100-pin and 144- pin
packages on page 54.
Start condition on page 630 updated. Note removed in Table 30: CAN1
alternate function remapping. Note added in Table 39: TIM4 alternate
function remapping.
In Section 8.4.2: AF remap and debug I/O configuration register
(AFIO_MAPR), bit definition modified for USART2_REMAP = 0. In
Section 8.4.3: External interrupt configuration register 1 (AFIO_EXTICR1),
bit definition modified for SPI1_REMAP = 0.
In Table 213: Important TPIU registers, at 0xE0040004, bit2 set is not
supported.
TRACE port size setting corrected in TPUI TRACE pin assignment on
page 976. Figure 13, Figure 15, Figure 16, Figure 17 and Figure 18
modified. Figure 14: Basic structure of a five-volt tolerant I/O port bit added.
Table 8.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
on page 152 added.
Bit descriptions modified in Section 16.4.5 and Section 16.4.6.
JTAG ID code corrected in Section 29.6.2: Boundary scan TAP on page 960.
Modified: Section 18.2: WWDG main features, Section 5.2: BKP main
features, Section 5.3.1: Tamper detection, Section 5.3.2: RTC calibration,
Section 21.3: USB functional description, Controlling the downcounter: on
page 405, Section 4.1.2: Battery backup domain, Section 8.2: Introduction.
ASOE bit description modified in Section 5.4.2: RTC clock calibration
register (BKP_RTCCR).
Doc ID 13902 Rev 9 983/995