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Secure digital input/output interface (SDIO) RM0008 Table 145. R3 response Bit position Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘111111’ Reserved [39:8] 32 X OCR register [7:1] 7 ‘1111111’ Reserved 0 1 1 End bit 20.5.5 R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content. Table 146. R4 response Bit position Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘111111’ Reserved [39:8] Argument field [31:16] 16 X RCA [15:8] 8 X register address [7:0] 8 X read register contents [7:1] 7 ‘1111111’ CRC7 0 1 1 End bit 20.5.6 R4b For SD I/O only: an SDIO card receiving the CMD5 will respond with a unique SDIO response R4. The format is: Table 147. R4b response Bit position Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 x Reserved 39 16 X Card is ready [38:36] 3 X Number of I/O functions [39:8] Argument field 35 1 X Present memory [34:32] 3 X Stuff bits [31:8] 24 X I/O ORC 492/995 Doc ID 13902 Rev 9
RM0008 Secure digital input/output interface (SDIO) Table 147. R4b response (continued) Bit position Width (bits Value Description [7:1] 7 X Reserved 0 1 1 End bit Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card. Note that an SD memory-only card may respond to a CMD5. The proper response for a memory-only card would be Present memory = 1 and Number of I/O functions = 0. A memory-only card built to meet the SD Memory Card specification version 1.0 would detect the CMD5 as an illegal command and not respond. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the card’s configuration based on the data contained within the R4 response. 20.5.7 R5 (interrupt request) Only for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0. Table 148. R5 response Bit position Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘111111’ CMD40 [39:8] Argument field [31:16] 16 X [15:0] 16 X [7:1] 7 X CRC7 0 1 1 End bit RCA [31:16] of winning card or of the host Not defined. May be used for IRQ data 20.5.8 R6 Only for SD I/O. The normal response to CMD3 by a memory device. It is shown in Table 149. Table 149. R6 response Bit position Width (bits) Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘101000’ CMD40 Doc ID 13902 Rev 9 493/995
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RM0008 Reference manual STM32F101xx
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RM0008 Contents 4.3.1 Slowing down
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RM0008 Contents 7.3.4 APB2 peripher
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RM0008 Contents 10.1 DMA introducti
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RM0008 Contents 12.3.2 DAC output b
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RM0008 Contents 13.4.6 TIM1&TIM8 ev
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RM0008 Contents 15.4.8 TIM6&TIM7 au
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RM0008 Contents 20 Secure digital i
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RM0008 Contents 21.5.2 Endpoint-spe
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RM0008 Contents 23.5.10 SPI registe
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RM0008 Contents 26.5 USB peripheral
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RM0008 Contents 27.7 Ethernet inter
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RM0008 List of tables List of table
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RM0008 List of tables Table 100. FS
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RM0008 List of tables Table 202. Pa
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RM0008 List of figures Figure 49. D
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RM0008 List of figures preloaded).
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RM0008 List of figures Figure 255.
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RM0008 Documentation conventions 1
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RM0008 Memory and bus architecture
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RM0008 CRC calculation unit 3.3 CRC
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RM0008 Power control (PWR) 4 Power
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RM0008 Power control (PWR) Note: Du
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RM0008 Power control (PWR) 4.3 Low-
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RM0008 Power control (PWR) Table 9.
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RM0008 Power control (PWR) switched
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RM0008 Power control (PWR) Bit 8 DB
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RM0008 Power control (PWR) 4.4.3 PW
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RM0008 Backup registers (BKP) 5.3 B
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RM0008 Backup registers (BKP) Bit 6
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RM0008 Backup registers (BKP) Table
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RM0008 Backup registers (BKP) Table
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RM0008 Low-, medium- and high-densi
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RM0008 Interrupts and events 9 Inte
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RM0008 Interrupts and events Table
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RM0008 Interrupts and events Table
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. RM0008 Interrupts and events 9.2.
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RM0008 Interrupts and events Figure
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RM0008 Interrupts and events 9.3.3
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RM0008 Interrupts and events 9.3.7
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RM0008 DMA controller (DMA) Figure
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RM0008 DMA controller (DMA) not sup
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RM0008 DMA controller (DMA) Table 5
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RM0008 DMA controller (DMA) 10.4 DM
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RM0008 DMA controller (DMA) 10.4.3
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RM0008 DMA controller (DMA) 10.4.5
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RM0008 DMA controller (DMA) Table 5
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RM0008 Analog-to-digital converter
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RM0008 Basic timers (TIM6&TIM7) 15
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RM0008 Basic timers (TIM6&TIM7) Fig
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Basic timers (TIM6&TIM7) 15.
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RM0008 Real-time clock (RTC) 16 Rea
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RM0008 Real-time clock (RTC) Figure
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RM0008 Real-time clock (RTC) 16.3.5
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RM0008 Real-time clock (RTC) RTC pr
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RM0008 Independent watchdog (IWDG)
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RM0008 Window watchdog (WWDG) Figur
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RM0008 Window watchdog (WWDG) 18.6
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RM0008 Device electronic signature
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RM0008 Debug support (DBG) Figure 3
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RM0008 Debug support (DBG) JTAG-DP
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RM0008 Debug support (DBG) DBGMCU_I
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RM0008 Revision history 30 Revision
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RM0008 Index ETH_MACMIIDR . . . . .
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RM0008 Please Read Carefully: Infor
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