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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Real-time clock (RTC)<br />

16 Real-time clock (RTC)<br />

Low-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 16 <strong>and</strong> 32 Kbytes.<br />

Medium-density devices are <strong>STM32F101xx</strong>, <strong>STM32F102xx</strong> <strong>and</strong> <strong>STM32F103xx</strong><br />

microcontrollers where the Flash memory density ranges between 64 <strong>and</strong> 128 Kbytes.<br />

High-density devices are <strong>STM32F101xx</strong> <strong>and</strong> <strong>STM32F103xx</strong> microcontrollers where the<br />

Flash memory density ranges between 256 <strong>and</strong> 512 Kbytes.<br />

Connectivity line devices are <strong>STM32F105xx</strong> <strong>and</strong> STM32F107xx microcontrollers.<br />

This section applies to the whole STM32F10xxx family, unless otherwise specified.<br />

16.1 RTC introduction<br />

The real-time clock is an independent timer. The RTC provides a set of continuously running<br />

counters which can be used, with suitable software, to provide a clock-calendar function.<br />

The counter values can be written to set the current time/date of the system.<br />

The RTC core <strong>and</strong> clock configuration (RCC_BDCR register) are in the Backup domain,<br />

which means that RTC setting <strong>and</strong> time are kept after reset or wakeup from St<strong>and</strong>by mode.<br />

After reset, access to the Backup registers <strong>and</strong> RTC is disabled <strong>and</strong> the Backup domain<br />

(BKP) is protected against possible parasitic write access. To enable access to the Backup<br />

registers <strong>and</strong> the RTC, proceed as follows:<br />

● enable the power <strong>and</strong> backup interface clocks by setting the PWREN <strong>and</strong> BKPEN bits<br />

in the RCC_APB1ENR register<br />

● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup<br />

registers <strong>and</strong> RTC.<br />

Doc ID 13902 Rev 9 387/995

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