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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Backup registers (BKP)<br />

5.3 BKP functional description<br />

5.3.1 Tamper detection<br />

The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or<br />

from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper<br />

detection event resets all data backup registers.<br />

Note:<br />

However to avoid losing Tamper events, the signal used for edge detection is logically<br />

ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before<br />

the TAMPER pin is enabled.<br />

● When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE<br />

bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while<br />

there was no rising edge on the TAMPER pin after TPE was set)<br />

● When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the<br />

TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled<br />

(while there was no falling edge on the TAMPER pin after TPE was set)<br />

By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper<br />

detection event occurs.<br />

After a Tamper event has been detected <strong>and</strong> cleared, the TAMPER pin should be disabled<br />

<strong>and</strong> then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.<br />

This prevents software from writing to the backup data registers (BKP_DRx), while the<br />

TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection<br />

on the TAMPER pin.<br />

Tamper detection is still active when V DD power is switched off. To avoid unwanted resetting<br />

of the data backup registers, the TAMPER pin should be externally tied to the correct level.<br />

5.3.2 RTC calibration<br />

For measurement purposes, the RTC clock with a frequency divided by 64 can be output on<br />

the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register<br />

(BKP_RTCCR).<br />

The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.<br />

For more details about RTC calibration <strong>and</strong> how to use it to improve timekeeping accuracy,<br />

please refer to AN2604 "<strong>STM32F101xx</strong> <strong>and</strong> <strong>STM32F103xx</strong> RTC calibration”.<br />

Doc ID 13902 Rev 9 67/995

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