STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Table 188. Ethernet pin configuration (continued)
MAC signals MII default MII remap RMII default RMII remap Pin Pin configuration
ETH_MII_RXD2 - RXD2 - - PD11 Floating input (reset state)
ETH_MII_RXD3 - RXD3 - - PD12 Floating input (reset state)
27.4 Ethernet functional description: SMI, MII and RMII
The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated
DMA controller. It supports both default media-independent interface (MII) and reduced
media-independent interface (RMII) through one selection bit (refer to AFIO_MAPR
register).
The DMA controller interfaces with the Core and memories through the AHB Master and
Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave
interface accesses Control and Status Registers (CSR) space.
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before
transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet
frames received from the line until they are transferred to system memory by the DMA.
The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of
configuration registers permit the user to select the wanted mode and features for the MAC
and the DMA controller.
Figure 284. ETH block diagram
AHB Bus
AHB Master interface
DMA
TX
DMA
FIFO
RX
DMA
FIFO
Media
Access
Control
MAC 802.3
RMII
Interface
MII
Select
MDC
AHB Slave interface
DMA
Control
& Status
Registers
Operation
Mode
Register
MAC
Control
Registers
MDIO
ai15620
27.4.1 Station management interface: SMI
The station management interface (SMI) allows the application to access any PHY registers
through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.
Doc ID 13902 Rev 9 841/995