29.01.2015 Views

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

General-purpose timer (TIMx)<br />

RM0008<br />

Figure 102. Counter timing diagram, internal clock divided by 1<br />

CK_INT<br />

CNT_EN<br />

Timer clock = CK_CNT<br />

Counter register<br />

31<br />

32 33 34 35 36 00 01 02 03 04 05 06 07<br />

Counter overflow<br />

Update event (UEV)<br />

Update interrupt flag (UIF)<br />

Figure 103. Counter timing diagram, internal clock divided by 2<br />

CK_INT<br />

CNT_EN<br />

Timer clock = CK_CNT<br />

Counter register<br />

0034 0035 0036 0000 0001 0002 0003<br />

Counter overflow<br />

Update event (UEV)<br />

Update interrupt flag (UIF)<br />

Figure 104. Counter timing diagram, internal clock divided by 4<br />

CK_INT<br />

CNT_EN<br />

TImer clock = CK_CNT<br />

Counter register<br />

0035 0036<br />

0000 0001<br />

Counter overflow<br />

Update event (UEV)<br />

Update interrupt flag (UIF)<br />

324/995 Doc ID 13902 Rev 9

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!