STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Bit 15 TGFMSCM: Transmitted good frames more single collision mask
Setting this bit masks the interrupt when the transmitted good frames after more than a single
collision counter reaches half the maximum value.
Bit 14 TGFSCM: Transmitted good frames single collision mask
Setting this bit masks the interrupt when the transmitted good frames after a single collision
counter reaches half the maximum value.
Bits 13:0 Reserved
Ethernet MMC transmitted good frames after a single collision counter
register (ETH_MMCTGFSCCR)
Address offset: 0x014C
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after a single collision
in Half-duplex mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFSCC
r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r
Bits 31:0 TGFSCC: Transmitted good frames single collision counter
Transmitted good frames after a single collision counter.
Ethernet MMC transmitted good frames after more than a single collision
counter register (ETH_MMCTGFMSCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after more than a
single collision in Half-duplex mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCC
r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r
Bits 31:0 TGFMSCC: Transmitted good frames more single collision counter
Transmitted good frames after more than a single collision counter
Doc ID 13902 Rev 9 925/995