STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

Ethernet (ETH): media access control (MAC) with DMA controller
RM0008
The application can select one of the 32 PHYs and one of the 32 registers within any PHY
and send control data or receive status information. Only one register in one PHY can be
addressed at any given time.
Both the MDC clock line and the MDIO data line are implemented as alternate function I/O
in the microcontroller:
● MDC: a periodic clock that provides the timing reference for the data transfer at the
maximum frequency of 2.5 MHz. The minimum high and low times for MDC must be
160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI
management interface drives the MDC clock signal low.
● MDIO: data input/output bitstream to transfer status information to/from the PHY device
synchronously with the MDC clock signal
Figure 285. SMI interface signals
STM32
802.3 MAC
MDC
MDIO
External
PHY
ai15621
SMI frame format
The frame structure related to a read or write operation is shown in Table 13, the order of bit
transmission must be from left to right.
Table 189.
Management frame format
Management frame fields
Preamble
(32 bits)
Start Operation PADDR RADDR TA Data (16 bits) Idle
Read 1... 1 01 10 ppppp rrrrr Z0 ddddddddddddddd Z
Write 1... 1 01 01 ppppp rrrrr 10 ddddddddddddddd Z
The management frame consists of eight fields:
● Preamble: each transaction (read or write) can be initiated with the preamble field that
corresponds to 32 contiguous logic one bits on the MDIO line with 32 corresponding
cycles on MDC. This field is used to establish synchronization with the PHY device.
●
●
●
●
●
Start: the start of frame is defined by a pattern to verify transitions on the line
from the default logic one state to zero and back to one.
Operation: defines the type of transaction (read or write) in progress.
PADDR: the PHY address is 5 bits, allowing 32 unique PHY addresses. The MSB bit of
the address is the first transmitted and received.
RADDR: the register address is 5 bits, allowing 32 individual registers to be addressed
within the selected PHY device. The MSB bit of the address is the first transmitted and
received.
TA: the turn-around field defines a 2-bit pattern between the RADDR and DATA fields to
avoid contention during a read transaction. For a read transaction the MAC controller
842/995 Doc ID 13902 Rev 9