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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

USB on-the-go full-speed (OTG_FS)<br />

Host detection of a peripheral connection<br />

Even if USB peripherals or B-devices can be attached at any time, the OTG_FS will not<br />

detect any bus connection until V BUS is no longer sensed at a valid level (over 4.75 V).<br />

When V BUS is at a valid level <strong>and</strong> a remote B-device is attached, the OTG_FS Core issues<br />

an host port interrupt triggered by the device connected bit in the host port control <strong>and</strong><br />

status register (PCDET bit in OTG_FS_HPRT).<br />

Host detection of peripheral a disconnection<br />

The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit<br />

in OTG_FS_GINTSTS).<br />

Host enumeration<br />

After detecting a peripheral connection the host must start the enumeration process by<br />

sending USB reset <strong>and</strong> configuration comm<strong>and</strong>s to the new peripheral.<br />

Before starting to drive a USB reset, the application waits for the OTG interrupt triggered by<br />

the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), which indicates that the bus is<br />

stable again after the electrical debounce caused by the attachment of a pull-up resistor on<br />

DP (FS) or DM (LS).<br />

The application drives a USB reset signaling (single-ended zero) over the USB by keeping<br />

the port reset bit set in the host port control <strong>and</strong> status register (PRST bit in<br />

OTG_FS_HPRT) for a minimum of 10 ms <strong>and</strong> a maximum of 20 ms. The application takes<br />

care of the timing count <strong>and</strong> then of clearing the port reset bit.<br />

Once the USB reset sequence has completed, the host port interrupt is triggered by the port<br />

enable/disable change bit (PENCHNG bit in OTG_FS_HPRT). This informs the application<br />

that the speed of the enumerated peripheral can be read from the port speed field in the<br />

host port control <strong>and</strong> status register (PSPD bit in OTG_FS_HPRT) <strong>and</strong> that the host is<br />

starting to drive SOFs (FS) or Keep alives (LS). The Host is now ready to complete the<br />

peripheral enumeration by sending peripheral configuration comm<strong>and</strong>s.<br />

Host suspend<br />

The application decides to suspend the USB activity by setting the port suspend bit in the<br />

host port control <strong>and</strong> status register (PSUSP bit in OTG_FS_HPRT). The OTG_FS Core<br />

stops sending SOFs <strong>and</strong> enters the suspended state.<br />

The suspended state can be optionally exited on the remote device’s initiative (remote<br />

wakeup). In this case the remote wakeup interrupt (WKUPINT bit in OTG_FS_GINTSTS) is<br />

generated upon detection of a remote wakeup signaling, the port resume bit in the host port<br />

control <strong>and</strong> status register (PRES bit in OTG_FS_HPRT) self-sets, <strong>and</strong> resume signaling is<br />

automatically driven over the USB. The application must time the resume window <strong>and</strong> then<br />

clear the port resume bit to exit the suspended state <strong>and</strong> restart the SOF.<br />

If the suspended state is exited on the host’s initiative, the application must set the port<br />

resume bit to start resume signaling on the host port, time the resume window <strong>and</strong> finally<br />

clear the port resume bit.<br />

26.6.3 Host channels<br />

The OTG_FS core instantiates 8 host channels. Each host channel supports an USB host<br />

transfer (USB pipe). The host is not able to support more than 8 transfer requests at the<br />

Doc ID 13902 Rev 9 705/995

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