STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet DMA operation mode register (ETH_DMAOMR)
Address offset: 0x1018
Reset value: 0x0000 0000
The operation mode register establishes the Transmit and Receive operating modes and
commands. The ETH_DMAOMR register should be the last CSR to be written as part of
DMA initialization.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DTCEFD
RSF
DFRF
Reserved
TSF
FTF
Reserved
TTC
ST
Reserved
FEF
FUGF
Reserved
RTC
OSF
SR
rw rw rw rw rs rw rw rw rw rw rw rw rw rw rw
Reserved
Bits 31:27 Reserved
Bit 26 DTCEFD: Dropping of TCP/IP checksum error frames disable
When this bit is set, the core does not drop frames that only have errors detected by the
receive checksum offload engine. Such frames do not have any errors (including FCS error) in
the Ethernet frame received by the MAC but have errors in the encapsulated payload only.
When this bit is cleared, all error frames are dropped if the FEF bit is reset.
Bit 25 RSF: Receive store and forward
When this bit is set, a frame is read from the Rx FIFO after the complete frame has been
written to it, ignoring RTC bits. When this bit is cleared, the Rx FIFO operates in Cut-through
mode, subject to the threshold specified by the RTC bits.
Bit 24 DFRF: Disable flushing of received frames
When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive
descriptors/buffers as it does normally when this bit is cleared. (See Receive process
suspended on page 897)
Bits 23:22 Reserved
Bit 21 TSF: Transmit store and forward
When this bit is set, transmission starts when a full frame resides in the Transmit FIFO. When
this bit is set, the TTC values specified by the ETH_DMAOMR register bits [16:14] are ignored.
When this bit is cleared, the TTC values specified by the ETH_DMAOMR register bits [16:14]
are taken into account.
This bit should be changed only when transmission is stopped.
Bit 20 FTF: Flush transmit FIFO
When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all
data in the Tx FIFO are lost/flushed. This bit is cleared internally when the flushing operation is
complete. The Operation mode register should not be written to until this bit is cleared.
Bits 19:17 Reserved
Doc ID 13902 Rev 9 939/995