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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Ethernet (ETH): media access control (MAC) with DMA controller<br />

If the received frame length/type field is less than 0x600 <strong>and</strong> if the MAC is programmed for<br />

the auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to<br />

the count specified in the length/type field, then starts dropping bytes (including the FCS<br />

field). If the Length/Type field is greater than or equal to 0x600, the MAC sends all received<br />

Ethernet frame data to Rx FIFO, regardless of the value on the programmed auto-CRC strip<br />

option. The MAC watchdog timer is enabled by default, that is, frames above 2048 bytes (DA<br />

+ SA + LT + Data + pad + FCS) are cut off. This feature can be disabled by programming the<br />

watchdog disable (WD) bit in the MAC configuration register. However, even if the watchdog<br />

timer is disabled, frames greater than 16 KB in size are cut off <strong>and</strong> a watchdog timeout<br />

status is given.<br />

Receive CRC: automatic CRC <strong>and</strong> pad stripping<br />

The MAC checks for any CRC error in the receiving frame. It calculates the 32-bit CRC for<br />

the received frame that includes the Destination address field through the FCS field. The<br />

encoding is defined by the following polynomial.<br />

Gx = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1<br />

Regardless of the auto-pad/CRC strip, the MAC receives the entire frame to compute the<br />

CRC check for the received frame.<br />

Receive checksum offload<br />

Both IPv4 <strong>and</strong> IPv6 frames in the received Ethernet frames are detected <strong>and</strong> processed for<br />

data integrity. You can enable the receive checksum offload by setting the IPCO bit in the<br />

ETH_MACCR register. The MAC receiver identifies IPv4 or IPv6 frames by checking for<br />

value 0x0800 or 0x86DD, respectively, in the received Ethernet frame Type field. This<br />

identification applies to VLAN-tagged frames as well. The receive checksum offload<br />

calculates IPv4 header checksums <strong>and</strong> checks that they match the received IPv4 header<br />

checksums. The IP Header Error bit is set for any mismatch between the indicated payload<br />

type (Ethernet Type field) <strong>and</strong> the IP header version, or when the received frame does not<br />

have enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20<br />

bytes are available in an IPv4 or IPv6 header). The receive checksum offload also identifies<br />

a TCP, UDP or ICMP payload in the received IP datagrams (IPv4 or IPv6) <strong>and</strong> calculates the<br />

checksum of such payloads properly, as defined in the TCP, UDP or ICMP specifications. It<br />

includes the TCP/UDP/ICMPv6 pseudo-header bytes for checksum calculation <strong>and</strong> checks<br />

whether the received checksum field matches the calculated value. The result of this<br />

operation is given as a Payload Checksum Error bit in the receive status word. This status<br />

bit is also set if the length of the TCP, UDP or ICMP payload does not match the expected<br />

payload length given in the IP header. As mentioned in TCP/UDP/ICMP checksum on<br />

page 857, the receive checksum offload bypasses the payload of fragmented IP datagrams,<br />

IP datagrams with security features, IPv6 routing headers, <strong>and</strong> payloads other than TCP,<br />

UDP or ICMP. This information (whether the checksum is bypassed or not) is given in the<br />

receive status, as described in the RDES0: Receive descriptor Word0 section. In this<br />

configuration, the core does not append any payload checksum bytes to the received<br />

Ethernet frames.<br />

As mentioned in RDES0: Receive descriptor Word0 on page 898, the meaning of certain<br />

register bits changes as shown in Table 193.<br />

Doc ID 13902 Rev 9 861/995

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