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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

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RM0008<br />

Debug support (DBG)<br />

Bits 31:22 Reserved, must be kept cleared.<br />

Bit 21 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted<br />

0: Same behavior as in normal mode.<br />

1: CAN2 receive registers are frozen.<br />

Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5)<br />

0: The clock of the involved timer counter is fed even if the core is halted, <strong>and</strong> the outputs<br />

behave normally.<br />

1: The clock of the involved timer counter is stopped when the core is halted, <strong>and</strong> the outputs<br />

are disabled (as if there were an emergency stop in response to a break event).<br />

Bit 16 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted<br />

0: Same behavior as in normal mode.<br />

1: The SMBUS timeout is frozen<br />

Bit 15 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted<br />

0: Same behavior as in normal mode.<br />

1: The SMBUS timeout is frozen.<br />

Bit 14 DBG_CAN1_STOP: Debug CAN1 stopped when Core is halted<br />

0: Same behavior as in normal mode.<br />

1: CAN1 receive registers are frozen.<br />

Bits 13:10 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=4..1)<br />

0: The clock of the involved Timer Counter is fed even if the core is halted.<br />

1: The clock of the involved Timer counter is stopped when the core is halted.<br />

Bit 9 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted<br />

0: The window watchdog counter clock continues even if the core is halted.<br />

1: The window watchdog counter clock is stopped when the core is halted.<br />

Bit 8 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted<br />

0: The watchdog counter clock continues even if the core is halted.<br />

1: The watchdog counter clock is stopped when the core is halted.<br />

Bits 7:5 TRACE_MODE[1:0] <strong>and</strong> TRACE_IOEN: Trace pin assignment control<br />

– With TRACE_IOEN=0:<br />

TRACE_MODE=xx: TRACE pins not assigned (default state)<br />

– With TRACE_IOEN=1:<br />

TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode<br />

TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a TRACEDATA size<br />

of 1<br />

TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a TRACEDATA size<br />

of 2<br />

TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a TRACEDATA size<br />

of 4<br />

Bit 4:3 Reserved, must be kept cleared.<br />

Doc ID 13902 Rev 9 973/995

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