STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
USB on-the-go full-speed (OTG_FS)
Bit 0 XFRC: Transfer completed interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the
USB, for this endpoint.
OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3,
where x = Endpoint_number)
Address offset: 0xB08 + (Endpoint_number × 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in Figure 268. The application must read this register when the OUT
Endpoints Interrupt bit of the Core interrupt register (OEPINT bit in OTG_FS_GINTSTS) is
set. Before the application can read this register, it must first read the Device all endpoints
interrupt (OTG_FS_DAINT) register to get the exact endpoint number for the Device
Endpoint-x interrupt register. The application must clear the appropriate bit in this register to
clear the corresponding bits in the OTG_FS_DAINT and OTG_FS_GINTSTS registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
B2BSTUP
rc_
w1
/rw
Reserved
OTEPDIS
rc_
w1
STUP
rc_
w1
Reserved
EPDISD
rc_
w1
XFRC
rc_
w1
Bits 31:7 Reserved
Bit 6 B2BSTUP: Back-to-back SETUP packets received
Applies to Control OUT endpoints only.
This bit indicates that the core has received more than three back-to-back SETUP packets for
this particular endpoint.
Bit 5 Reserved
Bit 4 OTEPDIS: OUT token received when endpoint disabled
Applies only to control OUT endpoints.
Indicates that an OUT token was received when the endpoint was not yet enabled. This
interrupt is asserted on the endpoint for which the OUT token was received.
Bit 3 STUP: SETUP phase done
Applies to control OUT endpoints only.
Indicates that the SETUP phase for the control endpoint is complete and no more back-toback
SETUP packets were received for the current control transfer. On this interrupt, the
application can decode the received SETUP data packet.
Bit 2 Reserved
Bit 1 EPDISD: Endpoint disabled interrupt
This bit indicates that the endpoint is disabled per the application’s request.
Bit 0 XFRC: Transfer completed interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the
USB, for this endpoint.
Doc ID 13902 Rev 9 771/995