STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and ...

RM0008
Serial peripheral interface (SPI)
23.3 SPI functional description
23.3.1 General description
The block diagram of the SPI is shown in Figure 207.
Figure 207. SPI block diagram
Address and data bus
Read
Rx buffer
MOSI
SPI_CR2
MISO
Shift register
LSB first
TXE RXNE
IE IE
SPI_SR
ERR
IE
0
0 SSOE
TXDM
AEN
RXDM
AEN
Tx buffer
BSY OVR MOD CRC
ERR 0 0 TXE RXNE
F
Write
SCK
Baud rate generator
BR[2:0]
Communication
control
0
1
Master control logic
LSB
FIRST
BIDI BIDI
MODE OE
SPE BR2 BR1 BR0 MSTR CPOL CPHA
CRC
EN
SPI_CR1
CRC
Next
DFF
RX
ONLY
SSM
SSI
NSS
ai14744
Usually, the SPI is connected to external devices through 4 pins:
● MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
● MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
● SCK: Serial Clock output for SPI masters and input for SPI slaves.
● NSS: Slave select. This is an optional pin to select master/ slave mode. This pin acts as
a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level and become slaves when
they are configured in NSS hardware mode.
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 208.
Doc ID 13902 Rev 9 589/995