Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-1 System control coprocessor register functions (continued)Function Register/operation Reference to descriptionL2 cache PLEcontrol andconfigurationPLE Internal Start Address c11, PLE Internal Start Address Register on page 3-147PLE Internal End Address c11, PLE Internal End Address Register on page 3-148PLE Channel Status c11, PLE Channel Status Register on page 3-150PLE Context ID c11, PLE Context ID Register on page 3-152L1 instructionand data cache,and TLB DebugL1 Instruction and Data cache, BTB,GHB, and TLB Debugc15, L1 system array debug data registers on page 3-163L2 unified cache L2 unified cache c15, L2 system array debug data registers on page 3-178SystemperformancemonitorPerformance monitoring c9, Performance Monitor Control Register on page 3-101 -c9, Interrupt Enable Clear Register on page 3-120a. Returns device ID code.3.1.2 System control and configurationThe purpose of the system control and configuration registers is to provide overallmanagement of:• Security Extensions behavior• memory functionality• interrupt behavior• exception handling• program flow prediction• coprocessor access rights for CP0-CP13.The system control and configuration registers also provide the processor ID. Some ofthe functionality depends on how you set external signals at reset.System control and configuration behaves in three ways:• as a set of flags or enables for specific functionality• as a set of numbers, values that indicate system functionality• as a set of addresses for processes in memory.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-5