Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-18 shows the results of attempted access for each mode.Table 3-18 Results of access to Auxiliary Feature Register 0 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Auxiliary Feature Register 0, read CP15 with:MRC p15, 0, , c0, c1, 3 ; Read Auxiliary Feature Register 03.2.11 c0, Memory Model Feature Register 0The purpose of the Memory Model Feature Register 0 is to provide information aboutthe memory model, memory management, cache support, and TLB operations of theprocessor.The Memory Model Feature Register 0 is:• a read-only register common to the Secure and Nonsecure states• accessible in privileged modes only.Figure 3-7 shows the bit arrangement of the Memory Model Feature Register 0.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0Reserved FCSE TCM PMSA VMSAAuxiliary Control RegisterOuter shareableCache coherenceFigure 3-7 Memory Model Feature Register 0 formatARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-35