Cortex-A8 R2P2.pdf - ARM Information Center

Level 2 Memory SystemControl Register. The internal start address defines the block of data transfer beginningat the 64-byte aligned address and ending when the number of cache lines is transferredto or from the L2 cache as defined by the internal end address.NoteThe number of lines is limited to the size of the L2 cache RAM way.If the direction bit indicates that data is being transferred into the L2 RAM, then the L2RAM cache way is loaded. However, if the software programmed the direction bit toindicate the transferring of data from the L2 RAM, then each address performs an L2RAM lookup. Any cache line found to be dirty is evicted from the L2 cache RAM.NoteIt is entirely possible that the L1 data cache contains the same line that is transferred bythe PLE engine to the external memory. Therefore it is possible for the line to becomevalid in the L2 cache as a result of an L1 eviction.During data transfers into the L2 cache RAM, any L2 cache RAM data present in adifferent L2 cache RAM way, other than the way specified by the L2 PLE ControlRegister bits [2:0], remain in the different way. The preload engine continues with thenext cache line to be loaded and the line is not relocated to the specified way.During transfers to or from the L2 cache RAM, if the PLE crosses a page boundary, ahardware translation table walk is performed to obtain a new physical address for thatnew page. All standard fault checks are also performed. If a fault occurs, the PLEsignals an interrupt on error. The PLE updates the L2 PLE Channel Status Register tocapture the fault status. The address where the fault occurred is captured in the L2 PLEInternal Start Address Register.When a PLE channel completes the transfer of the data block to or from the L2 cacheRAM, it signals an interrupt. This interrupt can be either secure, nDMASIRQ, ornonsecure, nDMAIRQ, if IC bit [29] in the L2 PLE Control Register is enabled. Inaddition, there might be an interrupt-on-error, nDMAEXTERRIRQ, indicated if thePLE aborts for any reason and if the interrupt-on-error bit is enabled.If you program the PLE to load data into the L2 cache RAM, the PLE transfers data tothe L2 cache RAM if the memory region type is cacheable. To determine the memoryregion type, the PLE performs a hardware translation table walk at the start of thesequence and for any 4KB page boundary. The PLE channel does not save any state forthe table walk. The translation procedure is for exception checking purposes and fordetermination of the memory attributes of the page. Any unexpected L2 cache RAMhits found when using the PLE are ignored for any type of data transfer.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 8-7