Cortex-A8 R2P2.pdf - ARM Information Center

Program Flow Prediction5.6 Operating system and predictor contextThe BTB does not have to be invalidated on a context switch, self-modifying code, orany other change in the VA-to-PA mapping.ARMv7-A specifies two branch prediction invalidation operations:• MCR p15, 0, Rx, c7, c5, 6 ; invalidate entire branch predictor array• MCR p15, 0, Rx, c7, c5, 7 ; invalidate VA from branch predictor arrayThese operations are not required to perform a context switch in the processor and areimplemented as NOPs. ARMv7-A generic context-switching or self-modifying codecan contain these operations without cycle penalty. These instructions can be enabledby setting the IBE bit in the Auxiliary Control Register to 1. See c1, Auxiliary ControlRegister on page 3-61 for details.5.6.1 Instruction memory barriersARMv7-A requires Instruction Memory Barriers (IMBs) after updates to certain CP15registers or CP15 operations. The processor flushes the pipeline to ensure that theinstructions following the given CP15 instruction are fetched in the new context. Inaddition, self-modifying code sequences must be preceded by an IMB. Therecommended means of implementing an IMB is the ISB instruction.The following prefetch flush instruction is from earlier versions of the ARMarchitecture. The processor supports this instruction, but its use is deprecated inARMv7-A.MCR p15, 0, Rx, c7, c5, 4ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 5-9