Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field FunctionTable 3-60 Translation Table Base Register 0 bit functions (continued)[2] P Read-As-Zero and ignore writes. This bit is not implemented on this processor.[1] S Indicates the translation table walk is to nonshared or to shared memory:0 = nonshared1 = shared.[0] C Indicates the translation table walk is inner cacheable or inner noncacheable:0 = inner noncacheable1 = inner cacheable.a. For an explanation of N, see c2, Translation Table Base Control Register on page 3-79.Attempts to write to this register in secure privileged mode when CP15SDISABLE isHIGH result in an Undefined Instruction exception, see Security Extensions writeaccess disable on page 2-46.Table 3-61 shows the results of attempted access for each mode.Table 3-61 Results of access to the Translation Table Base Register 0 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteSecure data Secure data Nonsecure data Nonsecure data Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.A write to the Translation Table Base Register 0 updates the address of the first leveltranslation table from the value in bits [31:7] of the written value, to account for themaximum value of 7 for N. The number of bits of this address that the processor uses,and the required alignment of the first level translation table, depends on the value of N,see c2, Translation Table Base Control Register on page 3-79.A read from the Translation Table Base Register 0 returns the complete address of thefirst level translation table in bits [31:7] of the read value, regardless of the value of N.To access the Translation Table Base Register 0, read or write CP15 c2 with:MRC p15, 0, , c2, c0, 0 ; Read Translation Table Base RegisterMCR p15, 0, , c2, c0, 0 ; Write Translation Table Base Register3-76 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E