Cortex-A8 R2P2.pdf - ARM Information Center

GlossaryByte-invariantIn a byte-invariant system, the address of each byte of memory remains unchangedwhen switching between little-endian and big-endian operation. When a data itemlarger than a byte is loaded from or stored to memory, the bytes making up that data itemare arranged into the correct order depending on the endianness of the memory access.The ARM architecture supports byte-invariant systems in ARMv6 and later versions.When byte-invariant support is selected, unaligned halfword and word memoryaccesses are also supported. Multi-word accesses are expected to be word-aligned.See also Word-invariant.Byte lane strobeCacheA signal that is used for unaligned or mixed-endian data accesses to determine whichbyte lanes are active in a transfer. One bit of this signal corresponds to eight bits of thedata bus.A block of on-chip or off-chip fast access memory locations, situated between theprocessor and main memory, used for storing and retrieving copies of often usedinstructions and/or data. This is done to greatly increase the average speed of memoryaccesses and so improve processor performance.See also Cache terminology diagram on the last page of this glossary.Cache hitCache lineA memory access that can be processed at high speed because the instruction or datathat it addresses is already held in the cache.The basic unit of storage in a cache. It is always a power of two words in size (usuallyfour or eight words), and is required to be aligned to a suitable memory boundary.See also Cache terminology diagram on the last page of this glossary.Cache line indexThe number associated with each cache line in a cache way. Within each cache way, thecache lines are numbered from 0 to (set associativity) -1.See also Cache terminology diagram on the last page of this glossary.Cache lockdownCache missCache setTo fix a line in cache memory so that it cannot be overwritten. Cache lockdown enablescritical instructions and/or data to be loaded into the cache so that the cache linescontaining them are not subsequently reallocated. This ensures that all subsequentaccesses to the instructions/data concerned are cache hits, and therefore complete asquickly as possible.A memory access that cannot be processed at high speed because the instruction/data itaddresses is not in the cache and a main memory access is required.A cache set is a group of cache lines (or blocks). A set contains all the ways that can beaddressed with the same index. The number of cache sets is always a power of two.See also Cache terminology diagram on the last page of this glossary.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-7