Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorThe PLE Internal End Address Register bits [N:6] contain the number of cache linestransferred where N is determined by the L2 cache size as defined in Table 3-130.Table 3-130 Maximum transfer size for various L2 cache sizesCache size N Maximum number of lines Maximum transfer size0KB 6 0 0KB a128KB 14 256 16KB256KB 15 512 32KB512KB 16 1024 64KB1024KB 17 2048 128KBa. For a 0KB cache, the PLE setup code must read the Cache Size ID Register, see c0,Cache Size Identification Registers on page 3-54, before attempting PLE access. In a0KB environment, the PLE does nothing.Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure AccessControl Register on page 3-73. The processor can access this register in User mode ifthe U bit for the currently selected channel is set to 1, see c11, PLE User AccessibilityRegister on page 3-139.Table 3-131 shows the results of attempted access for each mode.Table 3-131 Results of access to the PLE Internal End Address Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserUbitPLEbit Read Write Read Write Read Write Read Write0 0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined1 Data Data Data Data Undefined Undefined Undefined Undefined1 0 Data Data Undefined Undefined Data Data Undefined Undefined1 Data Data Data Data Data Data Data Dataa. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the PLE Internal End Address Register, set the PLE Channel Number Registerto the appropriate PLE channel and read or write CP15 with:MRC p15, 0, , c11, c7, 0 ; Read PLE Internal End Address RegisterARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-149