Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorLDR R1, =0x800000C0;MCR p15, 0, R1, c15, c3, 5;MRC p15, 0, R2, c15, c1, 0;Read I-HVAB into I-L1 Data 0 RegisterMove I-L1 Data 0 Register to R23.2.77 c15, L1 tag array operationsThe purpose of the L1 tag array operations is to:• read the L1 tag array contents and write into the system debug data registers• write into the system debug data registers and copy into the L1 tag array.The L1 tag array operation is accessible in secure privileged modes only. You cancalculate the value of N in Figure 3-73 and Figure 3-74 using the NumSets and LineSizefields as defined in Table 3-42 on page 3-56.Figure 3-73 shows the bit arrangement of the L1 tag array read operation.31 30 29 N+1 N 6 5 0AddressReserved Address ReservedAddressTagarrayFigure 3-73 L1 tag array read operation formatFigure 3-74 shows the bit arrangement of the L1 tag array write operation.L1 Data 0register31 23 220ReservedDataWrite data31 30 29 N+1 N 6 5 0ReservedAddressReservedAddressTagarrayAddressTo write one entry to the data side L1 tag array, for example:Figure 3-74 L1 tag array write operation formatLDR R0, =0x00500007;MCR p15, 0, R0, c15, c0, 0;Move R0 to D-L1 Data 0 RegisterARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-173