Cortex-A8 R2P2.pdf - ARM Information Center

GlossaryTrapTrigger instructionAn exceptional condition in a VFP coprocessor that has the respective exception enablebit set in the FPSCR register. The user trap handler is executed.The VFP coprocessor instruction that causes a bounce at the time it is issued. Apotentially exceptional instruction causes the VFP11 coprocessor to enter theexceptional state. A subsequent instruction, unless it is an FMXR or FMRX instructionaccessing the FPEXC, FPINST, or FPSID register, causes a bounce, beginningexception processing. The trigger instruction is not necessarily exceptional, and noprocessing of it is performed. It is retried at the return from exception processing of thepotentially exceptional instruction.See also Bounce, Potentially exceptional instruction, and Exceptional state.UnalignedUndefinedUNPUnpredictableUnpredictableVAVector operationA data item stored at an address that is not divisible by the number of bytes that definesthe data size is said to be unaligned. For example, a word stored at an address that is notdivisible by four.Indicates an instruction that generates an Undefined instruction trap. See the ARMArchitecture Reference Manual for more details on ARM exceptions.See Unpredictable.Means that the behavior of the ETM cannot be relied on. Such conditions have not beenvalidated. When applied to the programming of an event resource, only the output ofthat event resource is Unpredictable.Unpredictable behavior can affect the behavior ofthe entire system, because the ETM is capable of causing the core to enter debug state,and external outputs can be used for other purposes.For reads, the data returned when reading from this location is unpredictable. It can haveany value. For writes, writing to this location causes unpredictable behavior, or anunpredictable change in device configuration. Unpredictable instructions must not haltor hang the processor, or any part of the system.See Virtual Address.A VFP coprocessor operation involving more than one destination register, perhapsinvolving different source registers in the generation of the result for each destination.See also Scalar operation.VictimA cache line, selected to be discarded to make room for a replacement cache line that isrequired because of a cache miss. The way that the victim is selected for eviction isprocessor-specific. A victim is also known as a cast out.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-21