Cortex-A8 R2P2.pdf - ARM Information Center

Memory Management Unit6.7 MMU software-accessible registersTable 6-1 shows the CP15 registers that control the MMU. See Chapter 3 SystemControl Coprocessor for more information on CP15.Table 6-1 CP15 register functionsRegisterCross referenceTLB Type Register c0, TLB Type Register on page 3-28Control Register c1, Control Register on page 3-58Nonsecure Access Control Register c1, Nonsecure Access Control Register on page 3-73Translation Table Base Register 0 c2, Translation Table Base Register 0 on page 3-75Translation Table Base Register 1 c2, Translation Table Base Register 1 on page 3-77Translation Table Base Control Register c2, Translation Table Base Control Register on page 3-79Domain Access Control Register c3, Domain Access Control Register on page 3-81Data Fault Status Register (DFSR) c5, Data Fault Status Register on page 3-82Instruction Fault Status Register (IFSR) c5, Instruction Fault Status Register on page 3-85Data Fault Address Register (DFAR) c6, Data Fault Address Register on page 3-87Instruction Fault Address Register (IFAR) c6, Instruction Fault Address Register on page 3-88TLB operations c8, TLB operations on page 3-99TLB Lockdown Registers c10, TLB Lockdown Registers on page 3-128Primary Region Remap Register c10, Memory Region Remap Registers on page 3-132Normal Memory Remap Register c10, Memory Region Remap Registers on page 3-132FCSE PID Register c13, FCSE PID Register on page 3-158Context ID Register c13, Context ID Register on page 3-1616-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E