Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTo access the PLE Control Register, set the PLE Channel Number Register to theappropriate PLE channel and read or write CP15 with:MRC p15, 0, , c11, c4, 0 ; Read PLE Control RegisterMCR p15, 0, , c11, c4, 0 ; Write PLE Control RegisterWhile the channel has the status of Running, any attempt to write to the PLE ControlRegister results in architecturally Unpredictable behavior. For the processor, writes tothe PLE Control Register have no effect when the PLE channel is running.3.2.64 c11, PLE Internal Start Address RegisterThe purpose of the PLE Internal Start Address Register for each channel is to define thestart address, that is, the first address that data transfers go to or from.The PLE Internal Start Address Register is:• a 32-bit read/write register with one register for each PLE channel common toSecure and Nonsecure states• accessible in User and privileged modes.The PLE Internal Start Address Register bits [31:0] contain the Internal Start VirtualAddress (VA). Figure 3-57 shows this format.31 5 40virtual addressUNP/SBZFigure 3-57 PLE Internal Start Address Register bit formatAccess in the Nonsecure state depends on the PLE bit, see c1, Nonsecure AccessControl Register on page 3-73. The processor can access this register in User mode ifthe U bit for the currently selected channel is set to 1, see c11, PLE User AccessibilityRegister on page 3-139.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-147