Cortex-A8 R2P2.pdf - ARM Information Center

Signal DescriptionsTable A-3 MBIST interface (continued)SignalI/OResetDescriptionMBISTRESULTL2[2:0] O Undefined L2 MBIST controller status and data output:MBISTRESULTL2[0] = address expire flag or L2 MBISTDatalog Register outputMBISTRESULTL2[1] = fail flagMBISTRESULTL2[2] = test complete flag.MBISTUSERINL2[18:0] I - L2 MBIST configuration pins reserved for future expansion. Tiethese pins LOW.MBISTUSEROUTL2[4:0] O Undefined L2 MBIST configuration pins reserved for future expansion.Ignore these pins.CLK I - Clock input.ARESETn I - Reset input a .nPORESET I - Reset input a .a. Reset input is controlled in the same way during MBIST mode as during functional mode. See Reset domains onpage 10-5 for information on reset.A.3.2DFT pins and additional MBIST pin requirements during MBIST testingTable A-4 shows the signals necessary for DFT. It also shows the additional pinsrequired during MBIST testing.Table A-4 DFT and additional MBIST pin requirementsSignalI/OValue duringfunctional modeValue duringMBIST modeDescriptionMBISTMODEL1 I 0 1 Configures L1 for MBIST mode and disablesinstruction fetch after reset.MBISTMODEL2 I 0 1 Configures L2 for MBIST mode and disablesinstruction fetch after reset.TESTMODE I 0 0 Indicates ATPG test mode. Deassert duringMBIST mode.TESTCGATE I 0 1 Controls core clock gating during test modeor MBIST mode.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. A-5