Cortex-A8 R2P2.pdf - ARM Information Center

Design for Test11.1 MBISTThis section describes the array architecture and operation of the MBIST:• About MBIST• MBIST registers on page 11-3• MBIST operation on page 11-18• Pattern selection on page 11-24.11.1.1 About MBISTThe processor has three separate MBIST controllers:L1 and L2 MBIST controllersThe L1 and L2 MBIST controllers communicate with RAM arraysdistributed around the chip. Their controls are directly ported to theinterface for use with external testbench or Automated Test Equipment(ATE) drivers.CAMBIST controllerThe CAMBIST controller is a slave of the L1 MBIST controller. It targetsthe comparator logic of the Content-Addressable Memory (CAM). TheL1 MBIST controller tests the contents of the I-CAM and D-CAM arrays.The following arrays require MBIST support:• Instruction cache (I-cache)• Data cache (D-cache)• Global History Buffer (GHB)• Branch Target Buffer (BTB)• Translation Look-aside Buffer (TLB)NoteThe TLB has separate instruction and data arrays, each containing an attributearray, a CAM array, and a Physical Address (PA) array.• Hash Virtual Address Buffer (HVAB)• L1 tag RAM• all L2 cache RAM such as data, parity, tag, and valid RAMs.11-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E