Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field Function[31:19] - Reserved. UNP, SBZP.Table 3-58 shows how the bit values correspond with the Nonsecure Access ControlRegister functions.Table 3-58 Nonsecure Access Control Register bit functions[18] PLE Determines if an access to PLE registers is permitted in Nonsecure state:0 = PLE registers cannot be used in Nonsecure state1 = PLE registers can be accessed in both Secure and Nonsecure state.Nonsecure translation tables are used for address translation when the PLE bit is set to 1.[17] TL Determines if lockable translation table entries can be allocated in Nonsecure state:0 = lockable TLB entries cannot be allocated, reset1 = lockable TLB entries can be allocated.[16] CL Determines if lockdown entries can be allocated within the L2 cache in Nonsecure state:0 = entries cannot be allocated, reset value1 = entries can be allocated.If CL is set to 0, then any L2 cache lockdown operation takes an Undefined Instruction exception.[15:14] - Reserved. UNP, SBZ.[13:0] CP Determines permission to access the given coprocessor in the Nonsecure state, is the numberof coprocessor from 0 to 13:0 = secure access only, reset value1 = secure or nonsecure access.To access the Nonsecure Access Control Register, read or write CP15 with:MRC p15, 0, , c1, c1, 2 ; Read Nonsecure Access Control Register dataMCR p15, 0, , c1, c1, 2 ; Write Nonsecure Access Control Register dataTable 3-59 shows the results of attempted access for each mode.Table 3-59 Results of access to the Auxiliary Control Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Data Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.3-74 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E