Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s Model2.14 The program status registersThe processor contains one CPSR, and six SPSRs for exception handlers to use. Theprogram status registers:• hold information about the most recently performed logical or arithmeticoperation• control the enabling and disabling of interrupts• set the processor operating mode.Figure 2-12 shows the bit arrangements of the program status registers.31 30 29 28 27 26 25 24 23 20 19 16 15 10 9 8 7 6 5 4 0NZC V QJDNMGE[3:0]IT[7:2]EAIFTM[4:0]Greater thanor equal toJava state bitIT[1:0]Sticky overflowOverflowCarry/Borrow/ExtendZeroNegative/Less thanMode bitsThumb state bitFIQ disableIRQ disableImprecise abortdisable bitData endianness bitFigure 2-12 Program status registerNoteThe bits identified in Figure 2-12 as Do Not Modify (DNM) must not be modified bysoftware. These bits are:• Readable, to enable the processor state to be preserved, for example, duringprocess context switches.• Writable, to enable the processor state to be restored. To maintain compatibilitywith future ARM processors, and as good practice, you are strongly advised touse a read-modify-write strategy when you change the CPSR.2.14.1 The condition code flagsThe N, Z, C, and V bits are the condition code flags. You can set them by arithmetic andlogical operations, and also by MSR and LDM instructions. The processor tests these flagsto determine whether to execute an instruction.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 2-27