Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestTable 11-15 shows how each L2AdLSB[3:0] bit controls the increment and decrementsequence of the two column address LSBs.Table 11-15 Selecting counting sequence of L2 RAM column address LSBsL2AdLSB[n] LSB increment sequence LSB decrement sequence[0] 00, 01, 10, 11 11, 10, 01, 00[1] 00, 01, 11, 10 10, 11, 01, 00The reset value of the L2AdLSB[3:0] field is b0000.L2_ADDR_SCRAMBLE[289:0]Proper physical mapping prevents unintended pattern sequences that result in loss oftest quality. Use the ADDR_SCRAMBLE[289:0] field to define the physical-to-logicaladdress scramble setting for your implementation. See the Cortex-A8 Release Notes forinformation on how to program this for your design.L1 and L2 MBIST GO-NOGO Instruction RegistersYou can use the L1 and L2 MBIST GO-NOGO Instruction Registers to program acustom sequence of up to eight patterns for either L1 or L2 memory. Figure 11-3 showsthe fields of the L1 and L2 MBIST GO-NOGO Instruction Registers.NoteGO-NOGO on page 11-36 describes the default GO-NOGO sequence available atpower-up.In GNG1[10:0] GNG2[10:0] GNG3[10:0] GNG4[10:0] GNG5[10:0] GNG6[10:0] GNG7[10:0] GNG8[10:0]Figure 11-3 L1 and L2 MBIST GO-NOGO Instruction Registers bit assignmentsARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-13