Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor31 25 24 0FCSE PIDReservedBits Field FunctionFigure 3-64 FCSE PID Register formatTable 3-142 shows how the bit values correspond with the FCSE PID Registerfunctions.Table 3-142 FCSE PID Register bit functions[31:25] FCSE PID Holds the ProcID. Identifies a specific process for fast context switch. The reset value is 0.The purpose of the FCSE PID Register is to provide the ProcID for fast context switch memorymappings. The MMU uses the contents of this register to map memory addresses in the range0-32MB.[24:0] - Reserved. UNP, SBZP.Attempts to write to this register in secure privileged mode when CP15SDISABLE isHIGH result in an Undefined Instruction exception, see Security Extensions writeaccess disable on page 3-6.Table 3-143 shows the results of attempted access for each mode.Table 3-143 Results of access to the FCSE PID Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteSecuredataSecuredataNonsecuredataNonsecuredataUndefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.To access the FCSE PID Register, read or write CP15 with:MRC p15, 0, , c13, c0, 0 ; Read FCSE PID RegisterMCR p15, 0, , c13, c0, 0 ; Write FCSE PID RegisterTo change the ProcID and perform a fast context switch, write to the FCSE PIDRegister. You are not required to flush the contents of the TLB after the switch becausethe TLB still holds the valid address tags.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-159