Cortex-A8 R2P2.pdf - ARM Information Center

Design for Test• Bitmap test mode.Manufacturing test modeManufacturing test mode determines the pass or fail status of the arrays. If the failureflag is set to 1 when the complete flag is set to 1, you can retrieve the datalog to identifythe failing arrays. After analyzing the datalog, you can use bitmap test mode to identifythe failing bits.In manufacturing test mode, an MBIST test consists of the following steps:1. Assert MBISTMODE for the entire test.2. MBIST pipeline flush. Assert the system reset signal for at least 15 cycles.3. Instruction load. Write to the MBIST Instruction Register.4. Test execute. Wait for complete flag or fail flag.5. Datalog retrieval. If the fail pin, MBISTRESULT[1], is HIGH, read the MBISTDatalog Register.Bitmap test modeIn bitmap test mode, the MBIST controller stops when it detects a failure. It assertsMBISTRESULT[1] until the tester begins datalog retrieval. After datalog retrieval, theMBIST controller resumes the test from the point where it stopped. This handshakecontinues until test completion. The collected datalogs are useful for offline bitmap andredundancy analysis.In bitmap test mode, an MBIST test consists of the following steps:1. MBIST pipeline flush. Assert the system reset signal for at least 15 cycles.2. Instruction load. Write to the MBIST Instruction Register.3. Test execute.a. If failures are detected, go to step 4.b. If no failure is detected, go to step 5.4. Datalog retrieval. Go to step 3 to continue.5. End of test.MBIST Instruction loadFigure 11-7 on page 11-20 shows the timing of an MBIST instruction load. TheMBISTMODE signal must remain asserted while the core is under reset. SeeFigure 10-6 on page 10-6 for more information on reset timing. MBISTSHIFT isasserted and instruction load data is serially loaded into the Instruction Register throughthe MBISTDATAIN pin. MBISTSHIFT is deasserted on completion of the instructionload. MBISTDATAIN has one cycle of latency in relation to MBISTSHIFT.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-19