Cortex-A8 R2P2.pdf - ARM Information Center

AC Characteristics17.8 Miscellaneous signalsTable 17-8 shows the setup and hold times of miscellaneous signals not described in theprevious sections.Table 17-8 Timing parameters of miscellaneous signalsSignalClockSetupparameterPercent ofclock periodHoldparameternPORESET a,bCLK - - -ARESETn a,b CLK - - -ARESETNEONn a,b CLK - - -L1RSTDISABLE c CLK - - -L2RSTDISABLE c CLK - - -CLKSTOPREQ CLK - - -CLKSTOPACK CLK T ovclkstopack 30% T ohclkstopackSECMONOUTEN d CLK - - -SECMONOUT[86:0] CLK T ovsecmonout 30% T ohsecmonoutSTANDBYWFI CLK T ovstandbywfi 30% T ohstandbywfinFIQ a CLK - - -nIRQ a CLK - - -VINITHI c CLK - - -CFGTE c CLK - - -CFGEND0 c CLK - - -CFGNMFI c CLK - - -CP15SDISABLE CLK - - -CPEXIST[13:0] c CLK - - -SILICONID[31:0] c CLK - - -nPMUIRQ a CLK T ovnpmuirq 30% T ohnpmuirqa. This signal has multiple end-points and must be treated as level-sensitive.17-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E