Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorCWhen reading this register, any interrupt overflow enable bit that reads as 0 indicatesthe interrupt overflow flag is disabled. Any interrupt overflow enable bit that reads as 1indicates the interrupt overflow flag is enabled.When writing this register, any interrupt overflow enable bit written with a value of 0 isignored, that is, not updated. Any interrupt overflow enable bit written with a value of1 sets the interrupt overflow enable bit.Figure 3-46 shows the bit arrangement of the INTENS Register.31 304 3 2 1 0ReservedP3P2P1P0Figure 3-46 Interrupt Enable Set Register formatTable 3-102 shows how the bit values correspond with the INTENS Register functions.Table 3-102 Interrupt Enable Set Register bit functionsBitsFieldFunction[31] C CCNT overflow interrupt enable.[30:4] - Reserved. UNP, SBZP.[3] P3 PMCNT3 overflow interrupt enable.[2] P2 PMCNT2 overflow interrupt enable.[1] P1 PMCNT1 overflow interrupt enable.[0] P0 PMCNT0 overflow interrupt enable.Table 3-103 shows the results of attempted access for each mode.Table 3-103 Results of access to the Interrupt Enable Set Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserEN Read Write Read Write Read Write Read Write0 Data Data Data Data Undefined Undefined Undefined Undefined1 Data Data Data Data Undefined Undefined Undefined UndefinedARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-119