Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s ModelIn ARM state, you can execute most instructions conditionally on the state of the N, Z,C, and V bits. In Thumb state, you can execute fewer instructions conditionally.However, you can make most instructions conditional with the IT instruction.See the ARM Architecture Reference Manual for more information about conditionalexecutions.2.14.2 The Q flagYou can set the Sticky Overflow, Q flag, to 1 by executing certain multiply andfractional arithmetic instructions:• QADD• QDADD• QSUB• QDSUB• SMLAD• SMLAxy• SMLAWy• SMLSD• SMUAD• SSAT• SSAT16• USAT• USAT16.The Q flag is sticky in that, when set to 1 by an instruction, it remains set until explicitlycleared to 0 by an MSR instruction writing to the CPSR. Instructions cannot executeconditionally on the status of the Q flag.To determine the status of the Q flag, you must read the PSR into a register and extractthe Q flag from this. See the individual instruction definitions in the ARM ArchitectureReference Manual for details of how you can set and clear the Q flag.2.14.3 The IT execution state bitsIT[7:5] encodes the base condition code for the current IT block, if any. It contains b000when no IT block is active.IT[4:0] encodes the number of instructions that are to be conditionally executed, andwhether the condition for each is the base condition code or the inverse of the basecondition code. It contains b00000 when no IT block is active.2-28 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E