Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s ModelThis action restores the PC and CPSR, and returns to the instruction following the SVC.IRQs are disabled when a software interrupt occurs.2.15.9 Software Monitor InstructionWhen the processor executes the Secure Monitor Call (SMC) instruction, the core entersMonitor mode to request a Monitor function.NoteAn attempt by a User process to execute an SMC causes an Undefined Instructionexception.2.15.10 Undefined instructionWhen the processor encounters an instruction that neither it nor any coprocessor in thesystem can handle, it takes the Undefined Instruction exception. Software can use thismechanism to extend the ARM instruction set by emulating Undefined coprocessorinstructions.After emulating the failed instruction, the exception handler executes the followinginstruction, irrespective of the processor operating state:MOVS PC,R14_undThis action restores the CPSR and returns to the next instruction after the UndefinedInstruction exception.IRQs are disabled when an Undefined Instruction exception occurs. See the ARMArchitecture Reference Manual for more information about Undefined instructions.2.15.11 Breakpoint instructionA breakpoint, BKPT, instruction operates as though the instruction causes a prefetchabort. A breakpoint instruction does not cause the processor to take the prefetch abortexception until the instruction reaches the Execute stage of the pipeline. If the processordoes not execute the instruction, for example because a branch occurs while it is in thepipeline, the breakpoint does not take place.After dealing with the breakpoint, the handler executes the following instructionirrespective of the processor operating state:SUBS PC,R14_abt,#4This action restores both the PC and the CPSR, and retries the breakpointed instruction.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 2-41